Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
Several steps are common to most design flows for integrated microcircuits. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). As part of the creation of a logical design, a designer will also implement a place-and-route process to determine the placement of the various portions of the circuit, along with an initial routing of interconnections between those portions. The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
The “functional verification” begins with a circuit design coded at a register transfer level (RTL) being simulated by a design verification tool. A designer, for example, utilizing the design verification tool, can generate a test bench that can allow the design verification tool to analyze or verify the functionality of the simulated circuit design. Since it is often impractical to perform functional verification utilizing test benches that cover every possible operation for the simulated circuit design, many designers develop test benches that provide just a subset of possible input vectors to the simulated circuit design.
The design verification tool can attempt to identify how well those test benches came to covering or adequately exercising the simulated circuit design. Conventional techniques to determine test bench coverage of the circuit design include code coverage and functional coverage. Code coverage, such as statement coverage, decision coverage, condition coverage, expression coverage, or the like, can identify which lines, statements, expressions, decisions, in the code of the circuit design were exercised by the test bench during simulation. Functional coverage can quantify how well a test bench came to covering or adequately exercising functionality in the simulated circuit design. For example, a circuit design having a cache system can be deemed fully covered by conventional coverage techniques when each cache in the cache system enters every “legal” operational state in response to every “legal” event or transaction.